3- Bit Even And Odd Parity Generator

Description: Parity is a very useful tool in information processing in digital computers to indicate any presence of error bit information. To indicate any occurrence of error, an extra bit is included with the message according to the total number of 1’s in a set of data, which is called Parity. If the extra bit is considered 0 if the total number of 1’s is even and 1 for odd quantities of 1’s in a set of data, then it is called Even Parity. On the other hand, if the even bit is 1 for even quantities of 1’s and 0 for an odd number of 1’s, then it is called Odd Parity. After simplifying we get the expression as a) A XOR B XOR C for even parity b) Not (A XOR B XOR C) for odd parity Basically we need only two XOR gates, but to have both even and odd parity analyzed easily in one circuit we are adding an extra XOR gate. We are going to use the third XOR gate as control. We would also be using analog to digital and digital to analog converters. Procedure: Odd Parity Generator: Let us assume that we have a three-bit data sequence (B2B1B0) which needs to be communicated. we can find the expression for P in terms of B2, B1 and B0 as: Op = B2' B1' B0' + B2' B1 B0 + B2 B1' B0 + B2 B1 B0' = B2' (B1 AND B0) + B2 (B1 XOR B0) = B2 AND B1 AND B0 We can build an odd parity generator for three bits of data word using two XNOR gates. Even Parity Generator: Let us now design an even parity (EP) generator for two-bit data word B1B0. Thus we have: Ep = B1' B0 + B1 B0' = B1 XOR B0 Observation: Case 1: For odd parity, the number of ones in the bit stream sent (data bits in conjunction with parity-bit) has to be maintained as an odd number. That is, suppose we have our bit stream as 1001011, then the parity would be generated as 1 such that the number of ones in the resulting bit-stream (= 11001011) is 5, an odd number. Similarly, we can say that for the data sequence of 1001010, the parity-bit should necessarily be 0. Case 2: For even parity, the total number of ones in the bit stream, including the parity bit, becomes an even number. For example, if the data string is 1001011, then the parity-bit would be 0; while if it is 1001010, then parity-bit should be 1. Conclusion: Both even and odd parity generator is simulated and outputs are obtained. The characteristics of both even and odd parity generator are studied and analyzed. It is also observed here that how by changing the V4 i.e. DC voltage value we can transform the circuit to either even or odd parity generator. The message including the parity is transmitted and then checked at the receiving end of errors. Error is detected if the parity doesn’t correspond with the one transmitted. A parity generator is a combination logic system to generate the parity bit at the transmitting side.